The present invention relates to an arithmetic control unit which is provided with a plurality of processing elements having their own arithmetic functions, each processing element being operated in accordance with a microinstruction.
A conventional arithmetic control unit is shown in FIG. 1. A control section 10 is provided with a control storage 11 and various registers. The processing elements 20.sub.1, 20.sub.2, . . . , 20.sub.n have their own arithmetic functions. The processing elements 20.sub.1, 20.sub.2, . . . , 20.sub.n perform multiplication, fixed point addition/subtraction, and floating point addition/subtraction. The microinstruction bus 30 transfers a microinstruction read out from the control storage 11 in the control section 10. A data bus 40 transfers data from the registers in the control section 10 to the processing elements 20.sub.1, 20.sub.2, . . . , 20.sub.n , or transfers the operation results of the processing elements 20.sub.1, 20.sub.2, . . . , 20.sub.n to the registers in the control section 10. The data bus 40 actually comprises a data bus for the transfer of the operation result and a data bus for the transfer of source data, but is shown in a single line in the figure for the sake of simplicity. An element busy line 50 (hereinafter referred to as an EBSY line) is a transfer path of an element busy signal (hereinafter referred to as a signal EBSY) produced from the corresponding processing element 20.sub.i (i=1, 2, . . . , n) when a plurality of clock signals (system clock signals) are required for the processing of a single microinstruction in the processing elements 20.sub.i (i=1, 2, . . . , n). The signal EBSY is an inhibit signal for inhibiting the execution of the succeeding microinstruction and is transferred to the control section 10 through the EBSY line 50.
FIG. 2 shows interconnections of the control section 10 and the processing element 20.sub.i (i=1, 2, . . . , n) in FIG. 1. The microinstruction read out from the control storage 11 in the control section 10 is temporarily stored in an A microinstruction register 12 (hereinafter referred to as a MIRA) in response to a first timing clock signal CLK1 synchronized with the system clock signal CLK. Then, the microinstruction stored in the MIRA12 is output to the microinstruction bus 30. A register file 13 in which various data such as operation results are stored is provided in the control section 10. The designation of a register in the register file 13 is performed by the content of the predetermined field of the microinstruction which is output to the microinstruction bus 30. Then, the content of the register which is designated by the above microinstruction is output onto the data bus 40 from the register file 13. Furthermore, the microinstruction on the microinstruction bus 30 is distributed to individual processing elements 20.sub.i (i=1, 2, . . . , n).
A decoding section 21.sub.i is provided in the processing elements 20.sub.i for decoding the microinstruction which is distributed through the microinstruction bus 30. The decoding section 21.sub.i decodes the microinstruction (or a part of the microinstruction) from the microinstruction bus 30 to detect that the corresponding processing element 20.sub.i has been selected. Then the decoding section 21.sub.i provides the microinstruction (or the specified field of the microinstruction) to a B microinstruction register 22.sub.i (hereinafter referred to as a MIRB) and prohibits the succeeding input of the microinstruction from the microinstruction bus 30. This prohibition is cleared at the completion of the previous microinstruction execution. The microinstruction from the decoding section 21.sub.i is stored in the MIRB22.sub.i in response to the system clock signal CLK. At the same time, data on the data bus 40 are input to an arithmetic and logic unit 23.sub.i.
As apparent from the functions of the processing elements 20.sub.1, 20.sub.2, . . . , 20.sub.n , the processing element 20.sub.1 comprises a multiplier, the processing element 20.sub.2 comprises an adder and the processing element 20.sub.n comprises an adder and a shifter. The content of the MIRB 22.sub.i is output to the control circuit 24.sub.i to perform a mode designation for the arithmetic and logic unit 23.sub.i and the sequence control of the operation. The operation result from the arithmetic and logic unit 23.sub.i is output onto the data bus 40. The data (operation result) on the data bus 40 is stored in the specified register in the register file designated by the specified field of the microinstruction (on the microinstruction bus 30). Now the corresponding operation for one microinstruction is completed.
On the other hand, if the operation of the arithmetic and logic unit 23.sub.i is not completed within a single clock period (one system clock), the signal EBSY (effective at logical "0") is output onto the EBSY line 50 from the control circuit 24.sub.i. The signal EBSY on the EBSY line 50 is supplied to an inhibiting circuit 14 within the control section 10. A first inhibiting gate 15 for inhibiting the output of a first timing clock signal CLK1 for storing the microinstruction and a second inhibiting gate 16 for inhibiting the output of a second timing clock signal CLK2 for writing data in the register file are provided in the inhibiting circuit 14. The first inhibiting gate 15 is, for example an AND gate to control the system clock signal CLK, the signal EBSY used for the inhibition control and a signal 17 (which is actually a memory busy signal whose description is omitted for the sake of simplicity, since it is not directly related to the present invention). The AND gate 15 inhibits the system clock signal CLK to be output to the MIRA12 as the first timing clock CLK1 during the period when either the signal EBSY and/or the signal 17 is effective (logical "0"). Accordingly, when the signal EBSY of logical "0" is output onto the EBSY line 50 from the control circuit 24.sub.i of the processing element 20.sub.i, the supplement of the first timing clock signal CLK1 to the MIRA12 is inhibited by the first inhibiting gate 15. Therefore, the microinstruction fetch to the MIRA12 is prohibited, that is the execution of the microinstruction is prohibited. The second inhibiting gate 16 is, for example, an AND gate which receives the system clock signal CLK, the signal EBSY and a signal 18 which is a decoded signal of a so-called DNULL which designates information for prohibiting the storage of the operation result, i.e., a destination, into the register file 13. The second inhibiting gate inhibits the system clock signal CLK to be output to the register file 13 as a second timing clock signal CLK2 during the period when at least one of the signals EBSY or 18 is effective (logical "0").
FIGS. 3A through 3E are timing charts showing the above prior art operation, wherein a microinstruction M1, a microinstruction M2 and a microinstruction M3 are sequentially executed. The microinstruction M1 is, for example a multiplication instruction which requires a plurality of clock signals for the operation. The DNULL information described above is designated in the microinstruction M1 so that the multiplication result is not stored in the register file 13. In this example, the multiplication result is stored in the register file 13 in accordance with the command of the microinstruction M2. As is apparent from the above description, when the microinstruction M1 which requires a plurality of clock signal is executed, the effective signal EBSY is produced from the control circuit 24.sub.i of the corresponding processing element 20.sub.i. In this example, the signal EBSY is produced from the control circuit of the processing element 20.sub.1 for example, which has the multiplication function. The signal EBSY is continuously produced during the execution of the microinstruction M1. When the microinstruction M1 requires 6 clock signals (clock signal 1 through clock signal 6), the prohibiting functions of the first and second gates 15, 16 of the inhibiting circuit 14 are performed during the period of 6 clock signals. As a result, as shown in FIG. 3D, the output of the first timing clock signal CLK1 is inhibited and the storage of the succeeding microinstruction M2 read out from the control storage 11 into the MIRA 12 is prohibited. That is, the execution of other microinstructions is prohibited by the function of the inhibiting circuit under the control of the signal EBSY. At the clock signal 6, by which time the processing of the microinstruction M1 is completed, the control circuit 24.sub.i sets the signal EBSY to logical "1". Then the first inhibiting gate is released from the inhibiting condition and produces the first timing clock signal CLK1 again at the clock signal 7 and so on. On the other hand, the decode signal 18 corresponding to the DNULL information designated in the microinstruction M1 is input to the second inhibiting gate 16. Therefore, the gate 16 is released from the inhibiting condition and produces the second timing clock signal CLK2 at the clock signal following the clock signal 7 at which next microinstruction M2 is executed.
As apparent from the above description, in the prior art arithmetic control unit, the inhibiting circuit 14 functions under the control of the EBSY signal to prohibit the execution of the succeeding microinstruction during the execution of the microinstruction which requires a plurality of clock signals. This function is effective where the succeeding microinstruction uses the execution result of the microinstruction which requires a plurality of clock signals. To prohibit the execution of the succeeding microinstruction during the execution of the microinstruction which requires a plurality of clock signals, it is also useful to insert some dummy microinstructions, for example a no operation (NOP) microinstruction after the microinstruction which requires a plurality of clock signals. This method eliminates the inhibiting circuit 14. However, a disadvantage might be caused in that the capacity of the control storage 11 must increase since the dummy instructions have to be stored in a plurality of locations in the control storage 11.
As has been described, the prior art arithmetic control unit is so constructed that the inhibiting circuit 14 functions to inhibit the execution of the succeeding microinstruction during the execution of the microinstruction which requires a plurality of clock signals. Therefore, it has successfully avoided obtaining an erroneous operation result caused by the execution of the succeeding microinstruction during the execution of the microinstruction which requires a plurality of clock signals without using dummy instructions in a plurality of locatibns of the control storage 11, that is without increasing the capacity of the control storage 11.
However, the prior art system has a significant drawback in that the succeeding microinstruction is absolutely prohibited during the execution of the microinstruction which requires a plurality of clock signals by the inhibiting circuit 14 even if the parallel operation of the two microinstructions can be performed in the same cycle. This disadvantage obstructs the effective use of other processing elements and precludes high speed operation of the system.